Feeding the Leviathan: Data Center Power in the AI Compute Era
AI compute demand is rising at an extraordinary pace, roughly doubling every 4-6 months. Physically, this demand manifests as data centers. Their growth has become so aggressive that avoiding a capacity shortfall would require building more than twice the total capacity added since 2000, all within the next five years. The scale of what lies ahead is difficult to overstate.
This is not only a story about building more facilities. It’s also about a significant jump in density. Each new data center consumes far more power in far less space.
That shift creates pressure far beyond the walls of the data center. To support this growth, we must deliver significantly more power to many more places. Generation and transmission constraints are already slowing new builds, and access to behind-the-meter power generation has become a meaningful factor in site selection. Every watt matters, and nearly every layer inside the data center is being redesigned to extract more compute from the same power budget.
That’s a Lot of Watts
One of the clearest indications that something has changed is the unit of measurement itself. Data centers were once evaluated by real estate (square footage). Today, they are defined by power consumption (megawatts).
A decade ago, a hyperscale campus typically operated in the 30-50 MW range. Now, 200-500 MW campuses are the baseline, and projects like OpenAI’s Stargate or xAI’s Colossus are targeting gigawatt scale. In effect, we are attempting to deliver the energy output of a nuclear power plant into a warehouse.
Silicon is the primary catalyst behind this shift. AI-ready servers consume a lot more power than their traditional counterparts. While a legacy rack might consume 2-10 kW, an AI-dedicated rack pulls roughly 60 kW. And this will continue to rise: NVIDIA’s GB300 NVL72 rack-scale system peaks around 120kW. Since GPU/AI accelerator performance scales roughly linearly with transistor count and power consumption, this trajectory shows no sign of slowing.
Don’t Waste Power
Physics is a persistent constraint. Heat losses rise as more current pushes through conductors, making efficiency a core design priority.
Data center efficiency has improved rapidly in response. Historically, data centers operated at a Power Usage Effectiveness (PUE) of roughly 1.5, meaning that for every watt delivered to compute, another half-watt was consumed by cooling and other overhead. In a 500 MW facility, that level of inefficiency represents about 170 MW of lost energy—a small power plant’s worth of energy wasted. Cutting-edge facilities are now pushing PUE down to around 1.1.
The primary driver of this improvement has been the switch from air cooling to liquid cooling. Air cooling is limited to 30-40 kW per rack. With racks now surpassing 100 kW, liquid cooling has become essential. Direct-to-chip cold plates move heat far more effectively, allowing coolant loops to run warmer. This shift lets facilities avoid energy-intensive chillers for much of the year, instead relying on passive heat exchange. Thermal management technologies remain an active area of innovation and development, not just in active cooling and cold plate design, but also in the crucial material platforms that connect dies thermally to the outside world. All of these will need to continue scaling in parallel with rising chip power.
We’re Going to Need Bigger Pipes
The other half of the story is power delivery. Since PUE measurement usually stops at the server plug, losses inside the server and at the chip level are counted as compute, even though they do not contribute to useful work. At these levels of power consumption, delivering power to the transistors without thermal overload has become a key challenge.
Joule’s Law tells us that resistive losses scale with the square of the current. Double the current, quadruple the heat. Because electrical power is the product of voltage and current, increasing voltage is the most efficient way to deliver more power. This is the same principle behind high-voltage transmission lines. Data centers must bridge the gap between thousands of volts at the grid connection and roughly one volt at the transistor while minimizing losses at every step. Even with 95% efficiency per conversion stage, a standard six-stage topology loses about one quarter of total energy before it reaches the chip. In a 500 MW facility, recovering only 2% of those losses yields about 10 MW of additional compute capacity—that’s a lot of extra compute.
Here’s how the stack is being rewired:
- 48 V Racks. For decades, racks ran at 12 V. Delivering 100 kW at that voltage requires more than 8,000 Amps, which leads to expensive and unwieldy copper. Thus, the industry is moving quickly to 48 V, which cuts resistive losses by 16x and supports denser rack configurations1.
- High-Voltage DC and the move to 800 V. High-voltage DC distribution eliminates both inefficient AC-to-DC conversion stages2 and improves efficiency. While 400 V DC is emerging as a transitional standard, rising rack power densities have exposed the limits of this paradigm. The industry is poised to move to 800 V DC distribution to support the next wave of AI infrastructure.
- Wide Bandgap Semiconductors. As voltages rise, traditional silicon power devices reach their limits. Silicon carbide (SiC) and gallium nitride (GaN) have superior electrical properties and can switch faster with lower losses and better density. SiC devices will likely dominate closer to the grid in UPS systems3 and DC-to-DC conversion. GaN is better suited for the final stages of power delivery near the rack and the AI chip. While cost remains a barrier, scale and maturity will drive wider adoption.
- Integrated Voltage Regulators. The most critical battleground is the final inch between the motherboard and the silicon die. A single AI chip can draw more than 1 kW of power. Even a short path from the motherboard to the die can dissipate significant heat. Thus, on-board voltage regulators are giving way to an alternative approach: integrated voltage regulators (IVRs). IVRs step down voltage directly within the package or even inside the silicon itself. IVRs not only reduce resistive losses but also stabilize voltage during rapid workload spikes that would otherwise lead to voltage droop and system instability. We expect to see IVRs paired with vertical power delivery architectures to maximize their advantages, particularly when used with novel cooling designs (e.g., dual cold plates) that mitigate thermal challenges. IVRs are quickly becoming a must for next-generation AI silicon.
Looking Ahead
The data center power challenge is fundamentally a systems engineering problem that spans utilities, facilities, silicon design, and everything in between. No single technology will solve it, yet the opportunity for innovation across the entire value chain is enormous. As compute power continues its exponential climb, power delivery has become one of the most crucial areas of technological progress and investment to keep the AI wave unabated. The companies that solve some of these challenges stand to build transformational businesses.
If you are a founder working on these challenges, we want to hear from you!
1 You may be thinking: if 48V is better than 12V, why stop there? Many agree: the next step could be to raise the voltage of the rack to that of the power delivery network itself.
2 Transistors use DC, not AC, so there must be at least one AC-to-DC conversion from the grid to the chip.
3 UPS stands for Uninterruptible Power Supply. These are devices that provide near-instantaneous emergency power using stored energy (e.g., from batteries) to protect connected equipment from power interruptions and voltage anomalies, ensuring data center operation is not impacted by grid irregularities or brief blackouts.
